Referring to FIG. 1, a conventional dynamic random access memory cell 101 is shown. As shown, the memory cell comprises a cell transistor 110 and a cell capacitor 150 for storing information. A first junction 111 of the transistor is coupled to a bitline 125, and a second junction 112 is coupled to the capacitor 150. A gate electrode 113 of the transistor is coupled to a wordline 126. A reference or constant voltage (V.sub.pl) can be coupled to a plate of the capacitor. The plate which is coupled to the reference voltage can serve as a common plate in the memory array.
Cells are arranged in rows and columns to form an array, connected by wordlines in the row direction and bitlines in the column direction. The bitlines are coupled to sense amplifiers to facilitate memory accesses. Typically, a pair of bitlines is coupled to a sense amplifier. The bitline containing the selected memory cell is referred to as the bitline or bitline true and the other is referred to as the reference bitline or bitline complement.
The bitlines can be arranged in various types of bitline architectures, such as open, folded, open-folded, diagonal, multi-level, split-level, or split-level diagonal. Multi-level or split-level bitline architectures are described in, for example, Hamada et al., A Split Level Diagonal Bitline Stack Capacitor Cell for 256 Mb DRAMs, IEDM 92-7990, which is herein incorporated by reference for all purposes.
FIG. 2 shows a multi-level bitline architecture with vertical twists. As shown, a bitline pair 210 comprises bitlines 211 and 212 which occupy top and bottom bitline levels 230 and 220. The bitlines are vertically aligned with each other in the different bitline levels. Twists 280 are provided to switch the positions of the bitlines from the top to the bottom bitline level. The bitline segments occupying the bottom level comprise memory cells 250 coupled thereto. A memory access typically comprises precharging the bitlines to a predefined voltage level (e.g., equalization voltage or V.sub.bleq).
A memory cell within a bitline pair is selected after the bitlines are precharged and floated. The memory cell is selected by rendering the transistor of the memory cell conductive, coupling the memory cell's capacitor to the bitline true. Depending on the value stored in the capacitor, the bitline true is pulled above or below V.sub.bleq. The reference bitline, in the ideal case, remains at V.sub.bleq. The voltage difference between the reference bitline and bitline true is the differential voltage. A sense amplifier coupled to the bitline pair senses and amplifies the differential voltage signal, which is indicative of the data stored in the selected memory cell.
An important issue to consider in designing memory ICs is to provide an adequate sensing signal (i.e., differential voltage) to the sense amplifier in order for the data to be read accurately from memory. The differential signal sensed by a sense amplifier, in an ideal situation, depends on the charge sharing between the bitline and the memory cell. The ratio of the bitline capacitance (and the capacitance of the sense amplifier) to the cell capacitance determines the magnitude of the differential signal.
However, the voltage of the reference bitline increases or decreases along with the voltage swing on the bitline true due to bitline coupling between the bitlines of the bitline pair (intra-bitline coupling), thereby decreasing the magnitude of the differential signal or signal margin. For example, substantial coupling noise between the reference bitline in the upper level and the bitline in the lower level in the vertical twisted multi-level bitline architecture causes a decrease in the signal margin of the differential signal. A reduction in the signal margin of the differential signal is undesirable as this may lead to incorrect evaluation of the data stored in the memory cell.
In addition, coupling noise from neighboring bitline pairs (inter-bitline coupling) can also reduce the signal margin. The sense amplifiers of the array may not be activated simultaneously. This occurs as a result of, for example, different amplification speeds for a "0" and a "1", difference in the threshold voltage of the various latch transistors, or a skew in the activation of the sense amplifiers in the top and bottom bank in an interleaved arrangement. Coupling noise from a bitline pair whose differential signal is amplified can reduce the differential signal of a neighboring bitline pair whose differential signal has yet to be amplified.
The problems associated with coupling noise become worse as technology migrates to smaller groundrules due to the fact that the fraction bitline-to-bitline capacitance contribution to the total bitline capacitance increases with smaller dimensions
As evidenced from the foregoing discussion, it is desirable to reduce the impact of coupling noise.